Custom circuit designs are often prototyped within programmable logic devices (PLDs). One common type of PLD within which many circuit designs are prototyped is the field programmable gate array (FPGA). The high level of programmability offered by PLDs makes such devices well suited to development efforts. Generally, PLDs are a more costly option for implementing a circuit design once efforts move from development to production. Often, a standard cell implementation of the circuit design, e.g., an application specific integrated circuit (ASIC) implementation, is more cost effective in production than using a PLD.
To reduce costs, circuit designs initially developed using a PLD can be converted into standard cell circuit designs or structured standard cell circuit designs. The conversion process, however, involves several manual steps and can introduce errors into the resulting standard cell circuit design. For example, hard intellectual property (IP) cores available on the PLD, which are used by the PLD circuit design, are not available as standard cells. These cores typically are protected and unavailable to third parties. As such, replacement or alternate IP blocks must be manually selected for use in the standard cell circuit design.
In addition, the conversion process typically begins with a register transfer level (RTL) description of the PLD circuit design. The RTL circuit description is a high level circuit description that is above a gate-level description of the circuit design. The high level RTL description of the PLD circuit design undergoes the entire synthesis process using available timing constraints. The nature of some PLDs, e.g., FPGAs, is that many signal paths are not constrained. Unless manually or explicitly specified, the high level RTL is synthesized without timing requirements for such signal paths. In consequence, the standard cell circuit design may have significantly different timing characteristics than the PLD circuit design from which it was generated.